1. Field of the Invention
The present invention relates generally to imager chips and particularly to a method and apparatus for self-calibration and fixed-pattern noise removal in imager chips.
2. Description of the Related Art
In prior art imaging systems, one chip housed the light sensor circuitry and associated read out circuitry, while another chip housed the analog to digital (A/D) converter that converts an analog output signal of the first chip into a corresponding digital value that can be manipulated by a computer and stored. It is desirable that the A/D converters and signal processing functions be integrated into the imager chip. As is well known in the art, integration of functionalities of different chips into a single chip 1) reduces the system cost, and 2) decreases the space and power consumption of the product.
The imager portion of a complementary metal oxide semiconductor (CMOS) imager, i.e., imaging array, is essentially an analog circuit component. Heretofore, many other portions of the signal path have been implemented with analog circuits as well. The approach described here allows digital implementation of many of the functions which have previously been implemented in analog circuitry. Digital circuitry has two fundamental advantages; first, digital circuitry is more robust, denser, and easier to design than analog circuitry; and second, most fabrication capacity supports digital circuitry, due to its prevalence and ease of design. Further, cost is improved in that digital processes generally require fewer fabrication steps. However, this cost advantage is increased by the demands placed on the process by analog circuitry which requires better matching as well as expensive devices such as precision resistor layers, double-poly capacitors and silicide masks. Consequently, a circuit architecture which allows more functionality to be moved from the analog domain to the digital domain is desirable in terms of ease of design, manufacturability, and improved functional integration.
The integration of A/D converter is the first step to integrating other signal processing functions required by a camera system onto a single integrated circuit. There are two general approaches in integrating an A/D converter into an imager chip. The first approach is to employ an A/D converter for each column of the pixel array and perform the A/D conversion of the column values in parallel. A second alternative is to employ a single A/D converter for the entire array, and to perform the A/D conversion in series instead of in parallel. Both of these approaches have significant disadvantages and short comings that are now described.
In connection with employing multiple A/D converters (e.g., an A/D converter for each column of the pixel array), the key limitation with this approach is that the process and circuit mismatch between the A/D converters, particularly the comparators in the converters, causes fixed pattern noise on a column to column basis.
Fixed pattern noise is simply the difference in the output of two or more functionally identical circuits, such as A/D converters, when the same input is provided to the converters. This fixed pattern noise stems from differences in the individual A/D converter circuits, i.e., from excursions within the process tolerances. For example, a first A/D converter, coupled to a first column of the pixel array, can generate a first value when provided an input value. A second A/D converter, coupled to the last column of the pixel array, can have a second output value that is different from the first output value of the first A/D converter even when the same input value is provided to both converters. The mismatch of components and process on a column to column basis or on a pixel-to-pixel basis injects unwanted noise into the picture. For example, fixed pattern noise can cause an image to have column-wise stripes. Thus, the first approach requires well matched circuits, auto-zeroed comparators, or other means of removing the offsets between columns.
The second approach employing a single A/D converter for all the columns in the pixel array overcomes the circuit/process mismatch problem since the single A/D converter uniformly injects the same noise to all column values. However, this second approach has the following disadvantages: 1) has a limited bandwidth; and 2) requires an analog bus.
In connection with limited bandwidth, the second approach is limited in the amount of pixel information that it can produce over a period of time. For example, with a 640xc3x97800 pixel array, with each pixel represented by 10 bits, and a video rate of 30 frames per second, the imager chip must process approximately 15 million pixels per second. With a single A/D converter, that converter is required to produce a 10 bit result every 65 nanoseconds (ns). Two plausible candidates that can generate results at the above speed are 1) a flash A/D converter or 2) a pipelined A/D converter. To obtain a ten bit resolution from a flash A/D converter, one would require a very complex circuit that occupies an impractical amount of area. In other words, implementing such a flash A/D converter with ten bit resolution in an imager chip would be expensive and is not likely to be commercially practical. On the other hand, a pipelined A/D converter is very complex to implement.
Furthermore, this second approach requires an analog bus in the imager chip for communicating the analog values of each column to the A/D converter. The implementation of an analog bus on an imager chip increases circuit complexity and raises a host of difficult routing and noise issues since it is important that the analog values are maintained, i.e., guarded from noise so as to provide an accurate value to the A/D converter, which is often not proximal to the columns. Sending data at high fidelity across an analog bus may also limit the overall bandwidth, i.e., the frame rate of the entire imager. Additionally, the drivers from each column onto the bus must be matched to one another.
Furthermore, neither of these two approaches minimizes or addresses the fixed pattern noise of other circuits that are replicated per column for the entire array. For example, if an imager chip employs a correlated double sampling (CDS) circuit for each column to decrease the pixel-to-pixel fixed pattern noise, the CDS circuits themselves generate fixed pattern noise on a column by column basis. Thus additional circuitry may then be needed to reduce this column-to-column fixed pattern noise. The prior art employs a double differencing/sampling circuit (DDS), which is yet another analog circuit to address the fixed pattern noise generated by the CDS circuits. Consequently, neither of these two approaches optimally address the fixed pattern noise stemming from process/circuit mismatch, where optimality includes a measure of cost-effectiveness.
Accordingly, there remains a need in the industry for a method and apparatus that removes fixed pattern noise (stemming from column-to-column variations and from pixel-to-pixel variations in process/circuits) so that an imager chip having an integrated A/D converter architecture can be implemented without an analog bus and without expensive, high precision, high accuracy, analog components while minimizing fixed pattern noise. While the imager array is itself an analog block, moving as much functionality as possible across the boundary of the analog domain to the digital domain (recognizable by the A/D conversion point) is desirable.
A method and apparatus for self-calibration and noise removal in imager chips is disclosed. A storage device stores a digitized signal including an offset signal corresponding to noise. An analog-to-digital (A/D) converter digitizes a sample signal read from a pixel in a pixel array. A noise removal circuit receives the digitized sample signal and uses the digitized signal stored in the storage device to compensate for the noise in the digitized sample signal.